In an effort to improve interconnect speed, decrease power consumption and reduce integrated circuit package form factor, three-dimensional packages with die-to-die stacking has been promoted.
Die-to-die stacking minimizes the effort to place all technologies on a single die. Instead, multiple dies may be stacked together. Such dies may allow a different fabrication technology optimized for a particular type of circuitry, such as memory, logic, analog and sensors. Wide I/O memory is a recent dynamic random access memory (DRAM) technology that contemplates a memory die stacked on a microprocessor die or vice versa. JEDEC standard JESD229, “Wide I/O Single Data Rate,” December 2011, specifies four 128-bit channels, providing a 512-bit interface to DRAM. An interface between the dice involves, in one embodiment, solder connections.